1. Field of the Invention
This disclosure relates to a DRAM memory cell and more specifically, to a DRAM memory cell that prevents a short between storage node electrodes, and a method of manufacturing the same.
2. Description of the Related Art
As semiconductor devices become highly integrated and design rules become finer, it becomes more complicated to form patterns when manufacturing semiconductor devices. In DRAMs, even with finer patterns, the scaling of capacitances is hardly permitted. Thus, research directed at maximizing the capacitance within a small area has laboriously progressed.
Hereinafter, a method of manufacturing a conventional DRAM memory cell will be described with reference to FIGS. 1A through 1F, 2A through 2D, and 3A through 3D. FIGS. 1A through 1F are plan diagrams illustrating a method of manufacturing a conventional DRAM memory cell. FIGS. 2A through 2D are cross-sectional diagrams taken along line x–x′ of FIG. 1F, illustrating a method of forming storage node contact plugs. FIGS. 3A through 3D are cross-sectional diagrams taken along line y–y′ of FIG. 1F, illustrating the method of forming the storage node contact plugs.
Referring to FIG. 1A, a device isolation layer 11a is formed by a known method on a semiconductor substrate 10 to define active regions 11b where semiconductor devices will be formed. To dispose the greatest number of active regions 11b on the semiconductor substrate 10 within a limited area, parallel columns of the active regions 11b are formed on the semiconductor substrate 10 and every second column is disposed such that its active regions 11b correspond to gaps between active regions 11b in adjacent columns.
Referring to FIGS. 1B, 2A, and 3A, word line structures 12 are disposed on the semiconductor substrate 10. The word line structures 12 can extend perpendicularly to a lengthwise direction of the active regions 11b and be disposed such that a pair of word line structures 12 cross over one active region 11b. Impurity ions are implanted into the semiconductor substrate 10 on both sides of the active regions 12, thereby forming sources and drains (not shown). Next, a first interlayer dielectric (ILD) 13 is deposited on the resultant structure of the semiconductor substrate 10 and then etched until the sources and drains (not shown) are exposed, thereby forming contact holes (not shown). Here, the contact holes are formed in a self-aligned manner by means of the word line structures 12. Thereafter, the contact holes, formed in the first ILD 13, are filled with a conductive layer, for example, a doped polysilicon layer, to form first contact pads 14a and second contact pads 14b. Here, the first contact pads 14a contact the drains, while the second contact pads 14b contact the sources.
Continuing to refer to FIGS. 2A and 3A, a second ILD 16 is deposited on the first ILD 13. Next, the second ILD 16 is etched until the first contact pads 14a are exposed (see FIG. 1D). In FIG. 1D, reference character “A” refers to the exposed first contact pads 14a. A barrier metal layer 18, a metal layer 20 for bit lines, and a hard mask layer 22 are sequentially stacked on the second ILD 16 to contact the exposed first contact pads A. Afterwards, a photoresist pattern 24 is formed on the hard mask layer 22 to define bit line structures.
Next, as shown in FIGS. 2B and 3B, the hard mask layer 22, the metal layer 20 for the bit lines, and the barrier metal layer 18 are patterned in the shape of the photoresist pattern 24.
Next, as shown in FIGS. 1E, 2C, and 3C, bit line spacers 24 are formed by a known method on both sidewalls of the patterned hard mask layer 22, metal layer 20 for the bit lines, and barrier metal layer 18, thereby forming bit line structures 25. The bit line structures 25 are formed perpendicularly to the word line structures 12 and electrically contact the exposed first contact pads A. In FIG. 3C, which is a cross-sectional diagram taken in a direction parallel to the bit line structures 25, an entire bit line structure 25 is represented with dotted and solid lines. Also, in FIG. 3C, the reference character “DC” denotes a bit line contact region where a bit line 25 contacts a first contact pad 14a. A third ILD 27 is formed on the resultant structure of the semiconductor substrate 10 where the bit lines 25 are formed. Next, although not shown in the drawings, a photoresist pattern 29 is formed on the third ILD 27 so as to expose the second contact pads 14b. 
As shown in FIGS. 1F, 2D, and 3D, the third ILD 27 and the second ILD 16 are anisotropically etched using the photoresist pattern 29 as an etch mask, thereby forming storage node contact holes H (FIG. 2D). Once the storage node contact holes H are formed, the surfaces of the second contact pads 14b are exposed. In FIG. 1F, reference character “B” refers to the exposed surface of a second contact pad 14b. The storage node contact holes H are formed in a self-aligned manner by means of the bit line structures 25. In a view taken in a direction parallel to the word line structures 12, the storage node contact holes H are formed along the sidewalls of the bit line structures 25 (FIG. 2D), while in a view taken in a direction parallel to the bit line structures 25, they are formed in the shape of straight lines, as shown in FIG. 3D.
Thereafter, the storage node contact holes H are filled with a conductive material, thereby forming storage node contact plugs 30. Since each of the storage node contact plugs 30 is formed at each position “B” shown in FIG. 1F, the storage node contact plugs 30 are disposed densely such that one bit line 25 is interposed between every two storage node contact plugs 30. Next, as shown in FIGS. 2D and 3D, cylindrical storage node electrodes 35 are formed by a known method to contact the storage node contact plugs 30. The storage node electrodes 35 may be formed to be greater in size than the storage node contact plugs 30. As long as a short does not occur between adjacent storage node electrodes 35, the storage node electrodes 35 are formed to be as large as possible.
However, in the foregoing DRAM memory cell, the storage node electrodes 35 are bordered by the word line structures 12 and the bit line structures 25 and formed in a matrix shape. Thus, even a slight misalignment may cause a short between adjacent storage node electrodes 35. Further, as the diameter of a storage node electrode 35 is larger than that of a storage node contact plug 30, a short between adjacent storage node electrodes 35, which is referred to as “C” in FIG. 2D, is highly likely to occur.
Also, with an increase in capacitance of semiconductor devices, the storage node electrodes 35 must be larger in size. Thus, methods for expanding the sizes of the storage node contact plugs 30 and the storage node electrodes 35 have been developed. However, as shown in FIGS. 1F and 2D, extending the storage node contact plugs 30 and the storage node electrodes 35 in an X-axis direction is reaching the technical limit.
Further, as shown in FIGS. 1F and 2D, extending the storage node contact plugs 30 and the storage node electrodes 35 in a Y-axis direction may cause them to contact adjacent bit line contact region DC. Also, in this case, while the storage node contact holes H are being formed, the word line structures 12 may be damaged.
The foregoing problems hinder the manufacture of high-capacitance storage node electrodes. Embodiments of the invention address these and other problems in the conventional art.